With the wide application of the high voltage direct current transmission technology in the electrical power system, the reliability of the core part—the high voltage and high power thyristor valves become the key of the system safety. The default current test is concern to the thyristor valves design and fabrication level, and it is the important test method to improve its reliability. The main objective is to the design is right when the valves afford the maximum current, voltage and temperature stress result from short circuit current. At present, in the default current test the synthetic test concept is commonly used. And its basic idea is to use direct current source, default current source, high voltage source and so on, a sets of power system provides heating current, default current and the forward and reverse voltage for the converter valve, separately. The synthetic test circuit can complete the two following trials:
a) Subsequent locking single wave default current test inhibiting a maximum amplitude single wave default current, beginning with the highest temperature and then locking the forward and reverse voltage including any over voltage due to load rejection;
b) Non-subsequent locking multiwave default current test: under the same test condition to the single wave test, existing multi-wave default current before the breaker trips, but no more positive voltage supply.
At present, the high voltage source of the test circuit is consisted of L-C oscillation circuit, and the high voltage waveform is symmetrical. For the single wave default current test, the forward and reverse voltage amplitude provided for the test sample are same after the default current is off. But under the actual working condition, the test valve first gets reverse voltage and then the voltage reaches the positive maximum value and the reverse voltage peak value less than positive peak value after experiencing default current, the test valve temperature reduces gradually in the process. General speaking, the reverse over high voltage provided by the test circuit is very adverse for the valve that has withstood temperature default current, and that may damages the test valve. In addition, the time of the valve withstands positive voltage peak is after 5 ms the reverse voltage passed in actual working condition. For normal synthetic test circuit, in order to achieve the requirement must modify the circuit parameters, which results in the investment increase and test operation inconvenience.